The present invention relates to a VLSI (Very Large Scale Integration) integrated circuit having a significantly improved circuit density. More particularly, the invention pertains to such a VLSI circuit composed of a plurality of identical "multicells", each of which is identical to all other cells and each of which is composed of a number of transistors, diodes and resistors which are only partially interconnected prior to final device fabrication so that the various cells can be selectively configured in a desired logic circuit configuration and multiple ones of the cells can be connected together to implement any desired function. That is, the cells are not limited to any particular logic circuit configuration.
In general, to fabricate a VLSI device, a large chip, referred to as a "masterslice" is first produced. The masterslice will have formed thereon a number of logic circuits, typically OR, NOR, AND, NAND and EXCLUSIVE-OR gates, inverters, multiplexers, and the like. The book Integrated Circuits, A Basic Course for Engineers and Technicians, R. G. Hibberd, McGraw-Hill Book Company, 1969, pp. 136-142, gives a good general discussion of such devices. The master slices are stocked, and then later the various logic circuits thereon are wired together in a desired configuration to provide a logic circuit system which will perform a desired digital processing function.
This approach, although capable of yielding VLSI devices which will perform as desired, is nevertheless disadvantageous in that it is not possible to produce any one masterslice in which all of the logic circuits thereon can be used in all possible applications. That is, there is generally a relatively great waste of chip area because a large number of the logic circuits cannot be used in any given application.
U.S. Pat. No. 4,255,672 to Ohno et al. describes an improvement over the above-described basic technique wherein a plurality of identical emitter-coupled logic circuit cells are fabricated upon a single chip. In addition to the logic circuit cells, there are also fabricated upon the same chip a plurality of driver circuits composed of larger transistors having a greater drive capability than the transistors of which the logic circuit cells are composed. Although the approach of Ohno et al. may lead to some improvement in integration density, nonetheless, the approach suffers significant drawbacks in that the driver circuits take up a large portion of the overall available chip area. Also, complex wiring techniques must be employed to make connections between the ordinary logic circuit cells and the driver circuits since the positional inter-relationship between the logic circuit cells and the driver circuits cannot be optimum for all applications.
Accordingly, it is an object of the present invention to provide a VLSI integrated circuit in which maximum utilization is made of all circuit cells on the chip.
It is a further object of the invention to provide such a VLSI integrated circuit in which no complex wiring patterns are required to configure the logic circuit cells in the desired pattern.